Radiation-Hard Encryption FPGA

DSI provides its own IP Cores for performing encryption/decryption (AES, as well as elliptic curve-based algorithms), authentication (e.g. HMAC-RIPEMD-160, SHA-x), CCSDS-conformant channel coding/decoding, or SpaceWire interfaces according to ECSS-E-50-12A.

  • Implementation of the Advanced Encryption Standard (AES) according to the latest released documentation NIST FIPS PUB 197 with key length of 128 or 256 bits;
  • Support of different input and output port widths (e.g. 8, 16, 32, 64 or 128 bits)
  • Support encryption only, decryption only or encryption and decryption on one chip
  • Support for Xilinx Virtex families, Altera Stratix families, Actel ProAsic3, Actel AX FPGAs as well as other devices;
  • Support for different optimization goals such as implementation area or throughput
  • For detailed specifications please contact us